| 摘要 |
<p>PROBLEM TO BE SOLVED: To diminish error probability of the correspondence of a time stamp and a frame. SOLUTION: A packet decoder 32 extracts the time stamp of the head part of a packet which is the supply unit of data and a frame head detection part 33 detects the head of the frame which is the processing unit of the data. A control circuit 34 outputs frame reproduction timing signals T when the frame head detection signals FV (FA) of a poststage decoder are inputted and neglects the frame head detection signals FV (FA) for a fixed period after the frame head detection part 33 detects the head of the frame first after the time stamp is extracted. When the frame reproduction timing signals T are inputted, a comparison part 35 compares the time stamp with a standard timer and outputs synchronization control signals SV (SA) for allowing data output to the poststage decoder.</p> |
