| 摘要 |
PROBLEM TO BE SOLVED: To minimize the effects of dispersion in the oscillation frequency of a VCD on costs or productivity, while reducing jitter by operating a PLL circuit at the optimum frequency corresponding to the oscillation frequencies of the respective VCOS. SOLUTION: A reference signal for test and an actual operation time reference signal are inputted to a phase comparator 1, while being switched by a selector 7 under the control of a CPU 5. Further, the frequencies of the reference signal and an output from a frequency-divider circuit 4 are detected by a frequency detection circuit 6. When a PLL is operated at a frequency ft by the reference signal for test and a frequency dividing ratio is defined as N, at the time of PLL lock, the oscillation frequency of a VCO 3 is shown by ft×N and in the frequency of the output from the frequency-divider circuit 4, the same ft as the reference frequency is detected at the frequency detection circuit 6. This is stored in a memory 6 as frequency data characteristic to the VCO and at the time of the next ordinary operation, the PLL is operated at almost the center of oscillation frequency of the VCO 3, while reflecting the VCO frequency data stored in the memory 8. |
