发明名称 CIRCUIT AND METHOD FOR TESTING POWER-ON CLEARING
摘要 PROBLEM TO BE SOLVED: To reduce time for testing a power-on clear circuit and improve productivity. SOLUTION: A P-channel MOS transistor 1 and a capacitive element 2 are inserted in series between power supply potential and ground potential, while their series connection point A is connected to an input end of a voltage follower circuit 4 having an output control terminal 4 and a drain electrode of an N-channel MOS transistor 3 for connecting a source electrode to the ground potential, respectively, and an output of the voltage follower circuit 4 is connected to an output terminal 5. Output voltage of a power-on clear circuit is supplied to a gate electrode of the P-channel MOS transistor 1, a control signal for discharging held charge in the capacitive element 2 is supplied to a gate electrode of the N-channel MOS transistor 3, and an output enable signal for permitting an output is supplied to the output control terminal of the voltage follower circuit 4.
申请公布号 JPH1038982(A) 申请公布日期 1998.02.13
申请号 JP19960200667 申请日期 1996.07.30
申请人 NEC YAMAGATA LTD 发明人 TOKI KAZUHISA
分类号 G01R31/28;G06F11/22 主分类号 G01R31/28
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