| 摘要 |
As shown in the figure, a precharge halt access mode system reduces the power consumed during sequential accesses of the memory cells within a memory block. During sequential accesses to the memory cells within a row of the memory block in a synchronous system, the bitlines (306, 308, 310, 312) within the memory are only precharged after the memory access to the last memory cell within the row is complete. After access to the other memory cells within the row, the precharging operation for the bitlines (306, 308, 310, 312) within the memory block is halted by a halt precharge logic circuit. Once the memory access to the last column within the memory block is detected the precharging of the bitlines is performed. During sequential accesses to the memory cells within a row in an asynchronous system, the bitlines within the memory block are only precharged during an access to the first memory cell within a row.
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