发明名称 SIDE-WALL SPACER FOR VERTICAL CHROMIUM GATE LINES
摘要 <p>A method of depositing a thin conductive layer with improved step coverage during fabrication of a thin film transistor, comprising the steps of depositing a first layer of insulator material over a gate line which has been deposited and patterned on a glass substrate; removing planar portions of the first layer of insulator material via a reactive ion etch so as to expose portions of the glass substrate and gate line while introducing side-wall spacers of the insulator material which abut opposite side walls of the gate line; depositing a second layer of insulator material over the side-wall spacers and the exposed portions of the glass substrate and gate line, thereby forming a gate insulation layer having positively sloped portions overlying the side-wall spacers; and depositing the thin conductive layer over the gate insulation lyer, whereby the positively sloped portions of the gate insulation layer formed by the side-wall spacers result in conformal deposition of the thin conductive layer.</p>
申请公布号 WO1998006129(A1) 申请公布日期 1998.02.12
申请号 CA1996000519 申请日期 1996.07.31
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