摘要 |
<p>A solid state imager device such as a CCD imager device includes a timing generator which generates and supplies a clamping circuit with, a clamping pulse for clamping a first signal, corresponding to one pixel, from a through region of a CCD shift register, and a clamping pulse for clamping a second signal, corresponding to one pixel, from an optical black region of a sensor array. Specifically, the clamping pulse for clamping the first signal clamps a signal, corresponding to a first pixel, from the through region, and the clamping pulse for clamping the second signal clamps a signal, corresponding to a second or following pixel, from the optical black region. An output signal from the clamping circuit is supplied to an A/D converter which converts the supplied signal at such timing as not to clamp the signal, corresponding to the first pixel, from the through region. <IMAGE></p> |