TLB organization with variable page size mapping and victim-caching

摘要

A translation look-aside buffer (TLB) for translating a variable page size virtual page number to a physical page number. The TLB partitions the virtual page number into an upper portion and a lower portion. The upper portion is always compared to an upper virtual page number entry in a first content addressable memory while only certain bits of lower portion are selectively compared to a corresponding number of bits in a lower virtual page number entry in a second content addressable memory. The number of bits compared in the second content addressable memory is determined by the specified size of the physical page. The TLB includes a page size memory having a plurality of page size entries wherein the certain number of bits for each of the lower virtual page entries is specified by a corresponding page size entry. Associated with each bit in the lower virtual page number entries is an enable transistor for selectively enabling the comparison of that bit in the lower virtual page number entry. The enable gate includes a control input coupled to a corresponding bit in a corresponding page size entry, the enable transistor selectively enabling the single bit comparison when the corresponding bit in the page size entry is set to an enable state and selectively disabling the comparison when the corresponding bit in the page size entry is set to a disable state.