Fail analysis device for semiconductor memory test system

摘要

A fail analysis device is to count the number of fails with respect to a memory under test detected during the test. The fail analysis device includes: a fail memory for storing fail data regarding the memory under test in an address defined by address data from a memory test system when a fail signal is detected by a logic comparator; an OR circuit to provide input data to the fail memory based on an OR function between the fail signal from the logic comparator and data stored in the fail memory in an address defined by the address data; a write enable control for supplying an write enable signal to said fail memory based on the fail signal; an AND circuit which is provided with the fail signal from the logic comparator and the data stored in the fail memory in an address defined by the address data for transferring the fail signal when the data from the fail memory indicates that the fail data has not been stored in the address; and a fail counter for counting the number of the fail signal transferred from the AND circuit during a process of testing the memory under test by the memory test system.