发明名称 |
Output buffer incorporating shared intermediate nodes |
摘要 |
An output buffer is disclosed for an integrated circuit having a varying number of simultaneously switching outputs. As fewer outputs on the integrated circuit are simultaneously switching, the output conductance of certain logic gates within each of the output buffers on the integrated circuit is increased by sharing intermediate nodes between each of the output buffers. Consequently, the speed of the output buffer increases as fewer of the outputs simultaneously switch and internally generated noise is small. Conversely, as additional outputs simultaneously switch, the output conductance of certain logic gates within the output buffer is decreased, resulting in reduced speed of the output buffers and a corresponding reduction in internally generated noise.
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申请公布号 |
US5717342(A) |
申请公布日期 |
1998.02.10 |
申请号 |
US19960745410 |
申请日期 |
1996.11.22 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
LOTFI, YOUNES J.;PORTER, JOHN D. |
分类号 |
H03K19/0175;H03K19/003;(IPC1-7):H03K19/094 |
主分类号 |
H03K19/0175 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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