| 摘要 |
PURPOSE:To prevent the miswriting actions, the breakage, etc., of a memory cell by using a writing column selecting circuit containing a 3rd npn type transistor TR which is connected to the base of a 2nd TR of a writing circuit and conducts when the corresponding column selection signal has a low level to make the 1st and 2nd TRs of the corresponding writing circuit conduct respectively. CONSTITUTION:For instance, the gate circuits G2 and G1 of a row selecting circuit 2 are turned off and on respectively for selection of a row line X1. Then the inverters I1 and I2 are turned off and on with the column selection signals SY1 and SY2 together with a TRT5 and a TRT6 turned on and off respectively. Thus the writing circuits 3B and 3A are inactivated and activated respectively for selection of a memory cell M11. Under such conditions, a P-RM writing device 10 supplies a current of such a level that causes no write state to the cell M11 as a sense current. Thus both TRT1 and T2 are turned on since the TRT5 is already turned on. Then the current except the current to be supplied to the collector of the TRT5 flows to the circuit G1 of the circuit 2 kept in an ON state via the memory cell M11 out of the sense currents. Thus is is possible to prevent the miswriting actions, the breakage, etc., of the cell M11. |
