发明名称 |
Process for fabricating a stacked capacitor |
摘要 |
A method for fabricating a capacitor having a fin-shaped electrode on a dynamic random access memory (DRAM) cell having increased capacitance was achieved. The capacitor is fabricated on a silicon substrate having an active device region. The device region contains a metal-oxide-semiconductor field effect transistor (MOSFET), having one capacitor aligned over and contacting the source/drain of the MOSFET in the device region. The capacitor is increased in capacitance by forming a multilayer insulator structure over the storage capacitor area and recessing alternate layers, then using the form as a mold for forming a polysilicon fin-like bottom capacitor electrode. The remaining multilayer mold is removed and a high dielectric constant insulator is deposited on the bottom electrode as the inter-electrode dielectric. The top capacitor electrode is formed by depositing a doped polysilicon layer which also fills the recesses in the bottom electrode forming inter-digitized fin-shaped top and bottom capacitor electrodes and completing a dynamic random access memory (DRAM) cell.
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申请公布号 |
US5716884(A) |
申请公布日期 |
1998.02.10 |
申请号 |
US19960682403 |
申请日期 |
1996.07.17 |
申请人 |
UNITED MICROELECTRONICS CORPORATION |
发明人 |
HSUE, CHEN-CHIU;HONG, GARY;YANG, MING-TZONG |
分类号 |
H01L21/8242;(IPC1-7):H01L21/824 |
主分类号 |
H01L21/8242 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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