| 摘要 |
An apparatus and method for improving the execution speed of register generic micro instructions within a pipeline microprocessor is provided. The microprocessor includes descriptor compare logic which monitors references to last used segment registers, and maintains the base address of the last used segment. As holes are created by later register generic micro instructions, the descriptor compare logic compares operands with that of the last accessed segment register. When an operand of the present micro instruction is the same as the last accessed segment register, the descriptor compare logic provides a pipeline release signal which releases the base address associated with the last accessed segment register directly to the following stage in the pipeline, thereby effectively eliminating the register stage of the pipeline, and the associated hole in the pipeline, for the present micro instruction.
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