| 摘要 |
A memory array circuit has a matrix of column lines and row lines. A plurality of storage capacitors are arranged in the matrix, with each storage capacitor having a data node and a voltage node. Each of the plurality of storage capacitors has an associated column line and an associated row line, with the voltage node connected to the associated row line. A diode connects the data node of a storage capacitor to its associated column line. A first decoder decodes a first address signal and selects one of the column lines. A second decoder decodes a second address signal, and generates a row output signal, with each row output signal of the second decoder having a corresponding row line. A plurality of voltage control circuits is provided with each voltage control circuit receiving one of the plurality of row output signals, and for applying a control signal to a corresponding row line, in response to a data read signal, a data write to one state signal or a data write to another state signal.
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