| 摘要 |
<p>A programmable delay circuit comprises a number of parallel paths PATH0-PATH3 possessing different delays, a path being selected 3 by the programming code SEL. Due to manufacturing variations, the delays of the paths may not increase monotonically with the selection code. To restore a monotonic relation, the input code SEL is converted (figure 4) to a code SEL/A which selects paths of increasing delay, the code conversion relationship being determined by measurements of the actual delay of each path. The code conversion relation may be stored in RAM or writable ROM, or fixed by laser programming, and the code may be converted on the same IC as the delay circuit or outside it. The delay paths may comprise GaAs DCFL inverters with different fanout loads (figure 2b).</p> |
