发明名称 Device for and method of aligning in time digital signals, for example a clock signal and a data stream
摘要 <p>A device and a method for aligning in time two essentially isochronous digital signals are provided, in which a plurality (2&lt;n&gt;) of replicas (CK1-CK4) of the first signal (CKIN), separated by a given phase difference, are generated and a number of said replicas (CK3, CK4) is subjected to sampling (4, 5) in correspondence with the rising edges of the second signal (DATA). As the result of the sampling, a combination of logic signals (SLO, SL1) is obtained which is representative of the phase relation existing between each of said replicas (CK1-CK4) and the second signal (DATA). The output signal (CKOUT) of the device, aligned with the second signal, corresponds to the one, among the replicas (CK1- CK4) of the first signal, which best reproduces the desired alignment condition. &lt;IMAGE&gt;</p>
申请公布号 EP0822683(A2) 申请公布日期 1998.02.04
申请号 EP19970113112 申请日期 1997.07.30
申请人 CSELT 发明人 BOSTICA, BRUNO;BURZIO, MARCO;PELLEGRINO, PAOLO
分类号 G06F13/42;H03K5/00;H03K5/13;H04L7/02;H04L7/033;(IPC1-7):H04L7/033 主分类号 G06F13/42
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