FRACTION FREQUENCY DIVIDER AND PLL CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a PLL circuit capable of making the suppression of spurious noise and the enhancement of the lock-up speed compatible. SOLUTION: A phase shift circuit 27 generates plural phase shift signals FF whose phase is shifted respectively at a fixed angle at the same frequency as input signals fVCO based on the input signals fVCO. A selection circuit 28 successively selects the plural phase shift signals FF one by one based on selection signals S and outputs them. A frequency divider 29 frequencydivides the output signals X of the selection circuit 28 by the frequency division ratio of a prescribed integer. A selection signal generation circuit 32 generates the selection signals S based on the frequency division signals Pout of the frequency divider 29 and outputs them to the selection circuit 28. A counter circuit 35 outputs the count-up signals as fractional frequency division signals fp at the time of counting the prescribed number of the frequency division signals Pout of the frequency divider 29.