发明名称 |
Mean value detecting apparatus and mean value detecting integrated circuit having an offset voltage adjusting circuit |
摘要 |
Herein disclosed are a mean value detecting apparatus and a mean value detecting integrated circuit, having a mean value detecting unit formed with a resistance and a capacitance for detecting a mean value of an input signal, and an offset voltage adjusting unit connected in parallel to the mean value detecting unit at a connecting point of the resistance and a capacitance of the mean value detecting unit. With the above arrangement, this invention allows a large reduction of a size of the circuit.
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申请公布号 |
US5714895(A) |
申请公布日期 |
1998.02.03 |
申请号 |
US19950521689 |
申请日期 |
1995.08.31 |
申请人 |
FUJITSU LIMITED |
发明人 |
MORI, KAZUYUKI;KONDO, YOSHIHISA |
分类号 |
G01R19/00;G01R19/04;G06G7/12;(IPC1-7):H03D11/00 |
主分类号 |
G01R19/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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