| 摘要 |
In a trace control circuit for an emulation system, a program fetch signal is generated on the basis of a CPU read signal and a CPU program fetch status signal, both generated from the CPU included in the trace control circuit, and then, is thinned out at an arbitrary proportion so as to generate a trace memory write signal to a trace memory, so that a trace imformation outputted from the CPU is stored in a trace memory in response to the trace memory write signal thus generated. Accordingly, the memory capacity of the trace memory can be apparently increased.
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