| 摘要 |
PROBLEM TO BE SOLVED: To provide a DLL(delay locked loop) circuit without using the two systems of delay circuits. SOLUTION: This circuit is provided with correction clock generation circuits 2-5 for generating correction clock signals s3 for which a correction amount matched with the characteristics of an applied system is a pulse width and the delay circuit 8 for transmitting the correction clock signals s3 on many serially connected delay elements while delaying them. Further, a signal detection circuit for detecting a tap position where a first transition state is generated in the level of the correction clock signals s3 synchronized with external clock signals s1 by using signals outputted from many intermediate output taps provided for the respective prescribed intervals of the respective delay elements is provided inside respective delay blocks 8-1 -8-7 . In this case, by taking out the signals outputted from the tap position detected in the signal detection circuit as timing signals s7, without providing the two systems of the delay circuits, the timing signals to rise at a timing earlier than the rise of the external clock signals for the correction amount are generated. |
