| 摘要 |
The comparator circuit has a differential stage (D) forming a component of a cascade circuit (L,D,S,G) which has on one side of the differential stage a load stage (L) with load transistors (MN1,MP2) and on the other side a negative feed back stage (G). A reference voltage is applied both to the control electrode of a first load transistor (MN1), which has a high impedance input and supplies the voltage to be compared, and to the control electrode of a second load transistor (MP2). The first transistor represents a constant load impedance and a third load transistor (MP2) is connected in parallel with the second transistor which is switched on or off depending on signals from the comparator circuit. The result is that a further load impedance is either connected or not connected in parallel with the second transistor. |
