发明名称 Clock synchronization in data receivers
摘要 In a receiver for recovering digital data accompanied by synchronisation information and carried by radio signals, the radio signals are down converted at 2 and applied to a demodulator 5, 6 which generate frequency error and timing error data in dependence upon the demodulated signal, the synchronisation information and a clock signal. These error data on lines 19, 21 are used by a tracking circuit 20 and an adaptive filter 16 to control the frequency of a clock oscillator 14 included in a frequency control loop. The clock signal is applied to a divider chain 17 to apply clock signals to the down-converter 2, an A/D converter 4, a digital demodulator 5 and a DQPSK demodulator 6. The output of demodulator 6 is applied to a Viterbi decoder 22 via a demultiplexer 22. The receiver is used in a digital audio broadcasting arrangement and employs an orthogonal frequency division multiplexing modulation scheme in which the digital data is modulated onto a plurality of contemporaneously transmitted carrier frequency signals.
申请公布号 GB2315376(A) 申请公布日期 1998.01.28
申请号 GB19970013883 申请日期 1997.07.02
申请人 * ENSIGMA LIMITED;* ROKE MANOR RESEARCH LIMITED 发明人 DOMINIC THOMAS PARFREY * BANHAM;ADRIAN JOHN * ANDERSON
分类号 H04L27/26;(IPC1-7):H04L7/04 主分类号 H04L27/26
代理机构 代理人
主权项
地址