发明名称
摘要 <p>PURPOSE:To reduce the circuit scale of a microcomputer, by setting a data bus and an address bus at the outside, holding the transfer information at the transfer of the block data, and detecting the branch condition information via an arithmetic logic operation circuit to control the executing procedure. CONSTITUTION:When the transfer of the block data is started, the contents of Acc, X and Y registers 8a-8c are held in a stack. The origin of transfer address information is set at an SH register 8d and the X register 8b together with the transfer address information set a DH register 8e and the Y register 8c, and the length information on the block data set at an LH register 8f and the Acc register 8a respectively. The transfer data is written after output of the origin of transfer address. The origin of transfer address and transfer address are applied to a control circuit 13 as the branch condition information with operation of an arithmetic logic operation circuit 7 after the decision of transfer systems for increment, decrement, etc. Thus the transfer is possible with block data of various systems.</p>
申请公布号 JP2707256(B2) 申请公布日期 1998.01.28
申请号 JP19870214832 申请日期 1987.08.28
申请人 发明人
分类号 G06F13/38;G06F13/28;G06F15/78;(IPC1-7):G06F13/28 主分类号 G06F13/38
代理机构 代理人
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