Clock timing recovery circuit

摘要

In a clock timing recovery circuit for recovering the clock timing from a baseband signal obtained by detection of a received signal, clock timing is rapidly established by using a clock which has been phase-shifted from the desired clock timing to sample the baseband signal, and by obtaining the optimum phase from the sampled signal obtained as a result. A clock-timing recovery circuit according to this invention does not require oversampling and provides easy optimisation of circuit constants.