| 摘要 |
The present invention provides a DRAM cell comprising: an input/output bit line; a first word line being activated by a write control signal; a second word line being activated by a read control signal; a first transistor having a first terminal coupled to said input/output bit line, a second terminal, and having a gate electrode coupled to said first word line for coupling said first terminal to said second terminal responsive to said write control signal; and a second transistor having a gate electrode coupled to said second word line, a first terminal coupled to a reference voltage terminal, a second terminal coupled to said input/output bit line, and having a floating gate electrode coupled to said second terminal of said first transistor for coupling said first terminal to said second terminal responsive to said read control signal, wherein the voltage level of said input/output bit line is transferred to said floating gate, and wherein said first transistor varies the threshold voltage of said second transistor at a write operation and is turned off at a read operation, and said second transistor transfers the voltage level of said reference voltage terminal to said input/output bit line at said read operation and is turned off at said write operation.
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