| 摘要 |
A multiplier core circuit having a novel circuit configuration, which is preferable for LSI. The circuit contains a quadritail circuit formed of first, second, third and fourth transistors whose emitters or sources are coupled together. Collectors or drains of the first and fourth transistors are coupled together and collectors or drains of the second and third transistors are coupled together. A sum of first and second input signals to be multiplied is applied to a base or gate of the first transistor with regard to a reference point. The first input signal is applied to a base or gate of the second transistor with regard to said reference point. The second input signal is applied to a base or gate of the third transistor with regard to the reference point. Neither the first input signal nor the second input signal are applied to a base or gate of the fourth transistor. An output signal showing multiplication result of the first and second input signals is differentially derived between the collectors or drains of the first and fourth transistors and the collectors or drains of the second and third transistors.
|
