| 摘要 |
PCT No. PCT/DE94/00221 Sec. 371 Date Sep. 14, 1995 Sec. 102(e) Date Sep. 14, 1995 PCT Filed Mar. 1, 1994 PCT Pub. No. WO94/22079 PCT Pub. Date Sep. 29, 1994In order to be able to execute rapid processing of a program on super-scalar microprocessors, the individual instructions of this program must be divided into instruction groups, which can be processed by processing units of the microprocessor, in such a way that the instructions can be processed in parallel. In this case, it is necessary to take account of data-flow dependences and control-flow dependences as well as pipeline conflicts. For this purpose, the first step is to select the instructions whose precursor instructions have already been processed and to investigate these instructions as to whether before their execution a minimum number of delay cycles is necessary, and the instructions are stored with a minimum number in a list. From these instructions, one is selected using a heuristic selection process, and this one is classified into an instruction group in which the instruction can be processed in the earliest possible execution cycle.
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