Data loading circuit for partial program of nonvolatile semiconductor memory

摘要

The present invention provides a nonvolatile semiconductor memory comprising a plurality of floating gate-type memory cells arranged in a matrix form of rows and columns; a plurality of bit lines connected the memory cells arranged in the direction of said column; a plurality of data lines respectively connected to the plurality of bit lines; a plurality of latch circuits respectively connected to said plurality of data lines; a preset unit for presetting the plurality of latch circuits to predetermined logic states during a presetting operation; a unit for loading data to selected ones of the plurality of latch circuits through data input/output terminals during a data loading operation after the presetting operation; and unit for programming to the memory cells arranged and erased in one selected row, data loaded to the latch circuits of the selected portion and data presetted to remaining latch circuits except for the latch circuits of the selected portion during a programming operation after the data loading operation.