| 摘要 |
A super-voltage circuit with a fast reset capability is formed in an integrated circuit for generating a test mode logic state for testing other circuits in the same integrated circuit. The super-voltage circuit includes a sensing circuit, a reset circuit, and an output circuit connected to both the sensing circuit and the reset circuit. When the input voltage receives a super-voltage which is higher than either the logic high or low voltages, the sensing circuit generates at its output a high voltage. The reset circuit also receiving the same input voltage as the sensing circuit generates at its output a logic low state when the input voltage is at the super-voltage or logic high voltage. When the sensing circuit is generating the high voltage and the reset circuit is generating the logic low state, the output circuit generates at its output a logic low voltage. The logic low voltage signifies that the integrated circuit is now in the super-voltage test mode. To terminate the test mode, the super-voltage is removed from the input of the sensing circuit. As the input voltage falls to 0 volts, the reset circuit generates a logic high voltage. In response to the logic high voltage, the output circuit quickly resets its output to a logic high state signifying that the integrated circuit is now in a normal operational mode. |
