| 摘要 |
<p>PROBLEM TO BE SOLVED: To improve reliability in bit phase synchronization by controlling delay gates so as to permit signal delay quantites in the respective delay gates of a first delay gate group. SOLUTION: Input data Din is inputted to the first stage delay gate 21 of the first delay gate group 21. Then, the gate group 21 outputs delay data to a selector 23 concerning data Din, that is, data where the delay quantity is 0 and input data which are respectively outputted from the respective delay gates 211 -21n-1 . Therefore, the gate group 21 outputs n-kind of data strings with different phases to the selector 23. An input from the gate group 21 is executed to one of the respective inputs of the n-number two-input AND gates 251 to 25n of the selector 23 and n-number selecting signals are inputted to the other inputs without superimposition. The selector 23 selectively outputs one of n-kinds of data in the gate group 21 in accordance with the state of the selecting signals.</p> |
