| 摘要 |
A circuit and method for testing on-chip memory for a microprocessor or a microcomputer is disclosed. The memory test circuit includes an input register, an output register, an adder, and a sequencer to control the test process. The process includes receiving a simple communication protocol from the control unit to start the test, running a common memory test such as a checker board, AAAAh, 5555h and the like, and then storing the test results in an output register. The test circuit can include a bi-directional RESET signal means for disabling the system while the microprocessor or microcomputer runs its memory test.
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