发明名称 Method of making a semiconductor device having reduced junction capacitance between the source and drain regions and the substrate
摘要 A semiconductor device having a reduced junction capacitance of the source and drain and a method for manufacturing same. The method includes the steps of selectively forming an element separating region on a main surface of a <100> oriented semiconductor substrate of a first conductivity type, a step of providing a gate electrode on the region separated by the element separating region with an intervening insulating film, and a step of implanting impurities of a second conductivity type in regions under the source and drain regions using the gate electrode as a mask and with a predetermined angle of ion implantation to generate a channeling implantation condition.
申请公布号 US5712204(A) 申请公布日期 1998.01.27
申请号 US19950575475 申请日期 1995.12.20
申请人 NEC CORPORATION 发明人 HORIUCHI, TADAHIKO
分类号 H01L29/78;H01L21/265;H01L21/336;H01L21/8238;H01L29/10;(IPC1-7):H01L21/265 主分类号 H01L29/78
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