| 摘要 |
<p>PROBLEM TO BE SOLVED: To prevent delay for high speed data assigned in a frame cycle from being turned into the time of a multiframe unit, and to reduce it to the delaying time of a frame unit at the time of operating the phase correction of the data of a transmission path by a frame aligner in a data transmission system in a multiframe constitution, and controlling the reference of the phase correction by the multiframe unit. SOLUTION: High speed data in a frame cycle among input multiframe data are written in a memory 1, and low speed data in a multiframe cycle are written in a memory 2. Reading from the memories 1 and 2 is respectively operated in the frame cycle and the multiframe cycle in a device, and those memory outputs are derived according to a switch signal by a selection circuit 3, and reconstituted into the multiframe synchronizing with the multiframe cycle in the device, and outputted.</p> |
