| 摘要 |
PROBLEM TO BE SOLVED: To obtain an adder small in circuit scale by fully adding serially outputted data and carry inputs and delaying the carry of the result of full addition by a prescribed time to supply it as the carry input of a full adder. SOLUTION: A 1-bit full adder 150 inputs data outputted from input shift registers 110 and 120 in adding terminals A and B, inputs a carry input to a terminal C, fully adds them to output the carry from a terminal C and to output an adding result from a terminal S. A full adder with a carry storing function 140 outputs data (carry output) of an input terminal D by one clock according to a second control clock CKS given from a reset terminal (R) resetting the output Q of itself according to a first controlling clock CKP and a terminal CK. Then an output register 130 successively and serially fetches an adding result S from the side of LSB according to the second control clock CKS. |
