发明名称 IMAGE DESCRAMBLE CIRCUIT
摘要 PROBLEM TO BE SOLVED: To differentiate ciphering degree of image information for each reception station and to prevent illegal decoding by incorporating a random number generating circuit and a circuit for setting an initial state to be an optional value in an integrated circuit. SOLUTION: An initial value is set to a 1st address generating circuit ADH 9 so that head data of scramble data are a switching point by using a random number generating circuit 7, an address is given to a 1st memory circuit 16 through a 1st selection circuit 12 and data by one horizontal period are written through a 3rd selection circuit 14. Data are read from the circuit 16 according to a 2nd ADH 10 for a succeeding period and outputted to an output terminal 6 through the circuit 14, an initial value is set to the circuit 9 by using the circuit 7 and an address is given to a 2nd memory circuit through a 2nd selection circuit 13 and data are written through a 4th selection circuit 15. Data are read from a circuit 17 according to the circuit 10 for a succeeding horizontal period and outputted to the output terminal 6 via the circuit 15 and the circuit 7 is used to set an initial value to the circuit 9 and an address is set to the circuit 16 to write data by one horizontal period.
申请公布号 JPH1023389(A) 申请公布日期 1998.01.23
申请号 JP19960176059 申请日期 1996.07.05
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 TAKENO KOJI;KAWASHIMA ICHIRO;YAMADA YUTAKA
分类号 G06F21/10;H04N21/4405 主分类号 G06F21/10
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