| 摘要 |
PROBLEM TO BE SOLVED: To provide a testing circuit for reducing the number of testing terminals and test time required for the test of an arithmetic unit which operates data of a memory incorporated in LSI. SOLUTION: A test clock is inputted from an external input terminal 301 and test ROM address signals 311 and 312 are generated by couters 303 and 305 by the clock generated by a clock generating circuit 306. Then, data of ROM 316 and 317 as against the generated address are outputted to an adder 318. The coincidence of the addition result of the adder 318 with data of a serial/parallel conversion register 207, which is obtained by latching the expectation value of the addition result inputted from the external input terminal 302 is detected by a coincidence circuit 319 so that testing is executed in the adder and ROM. |
