SAMPLE-AND-HOLD CLOCK SYNTHESIS

摘要

PROBLEM TO BE SOLVED: To generate a sample and a clamp clock signal for a correlation duplex sampling with an excellent phase relation to the output of an imaging processor by identifying artifact of a reset signal. SOLUTION: A reset clock identified by a reset identification device 41 is given to a phase locked loop(PLL) 42. A voltage controlled oscillator(VCO) 51 multiplies 4 with its input and a prescaler 53 divides a clock signal received from the VCO 51 by 4. Then the divided clock signal is given to a phase discrimination device 52. The phase discrimination device 52 adjusts properly the phase relation of both clock signals. Then a signal filtered by a filter 54 is fed to the voltage controlled oscillator 51 to properly identify 1/4 of the video signal given to a clock generator 59. Then the sample and the clamp clock signal from the clock generator 59 are applied to a correlation duplex sampling device.