| 摘要 |
PROBLEM TO BE SOLVED: To display interpolation calculation accompanying the magnification or reduction of a texture pattern onto a mapping plane by hyperboric cubic correlation function, etc., on a high-speed arithmetic circuit in real time at the time of texture mapping. SOLUTION: A high-speed expansion/reduction transforming operation circuit for a source pattern is constituted by providing circuit configuration so that the texture pattern is read from a cache memory 2 in a texture address generating circuit 1 and data is loaded form an external memory 3 when cache error is detected by a cache error detection circuit 4 and by using an interpolation circuit 4 based on the hyperboric cubic function. |
