发明名称 FAULTY PLACE DISPLAYING METHOD FOR INTEGRATED CIRCUIT AND FAULTY PLACE DISPLAY DEVICE EXECUTING THE METHOD
摘要 PROBLEM TO BE SOLVED: To efficiently specify a circuit pattern or a logic circuit being a faulty spot by executing weighting of a faulty degree to a wire arranging coordinate matching a fault defining spot so as to specify a fault generating place. SOLUTION: A faulty spot extraction part 12 inputs fault analysis result information 21a from a data base for analyzing a fault 22 through a fault information input means 31 and sends it to a weighting means 33. In addition the part 12 inputs layout information 23a from a CAD layout device 23 through a layout result input means 32 and sends it to a weighting means 33. Next the means 33 inputting these pieces of information 21a and 23a executes the weighting of the fault degree by a designing condition for an arranged wiring coordinate 33a matching each fault defining spot and outputs the arranged wiring coordinate 33a coincident with each fault defining spot and weighting information 33b in a comment entering means 34. Then a file storing means 35 stores an arranged wiring coordinate 34a with weighting information.
申请公布号 JPH1021284(A) 申请公布日期 1998.01.23
申请号 JP19960174931 申请日期 1996.07.04
申请人 MITSUBISHI ELECTRIC CORP;MITSUBISHI DENKI SEMICONDUCTOR SOFTWARE KK 发明人 INOUE TAKAFUMI
分类号 G01R31/28;G06F11/22;G06F17/50 主分类号 G01R31/28
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