发明名称 CLOCK GENERATOR
摘要 PROBLEM TO BE SOLVED: To improve frequency stability of STC(system time clock) in an MPEG (moving picture expert group). SOLUTION: Multiplexed data S15 is separated into voice coded data Da, coded picture data Dv and PCR (time reference signal) by a system decoder 32. PCR is inputted to a pulse generator circuit 33, a jitter filter circuit 34 and a phase comparator 35. The circuit 33 generates a control pulse S33 at the time of receiving PCR. The jitter on the control pulse S33 is reduced by the circuit 34. Then the output pulse S34 of the circuit 34 is inputted to the comparator 35 as an operation timing pulse S36 through a 1/N frequency divider 36. The comparator 35 reads the value of PCR and the counted value S41 of a counter 41 at the time of the starting of the pulse S36 and outputs the difference as phase difference data S35.
申请公布号 JPH1022987(A) 申请公布日期 1998.01.23
申请号 JP19960178081 申请日期 1996.07.08
申请人 OKI ELECTRIC IND CO LTD 发明人 FUKUI KIYOSHI;NONAKA MASAHITO
分类号 H04N19/70;H04L7/00;H04L12/28;H04L12/70;H04N7/24;H04N19/00;H04N19/80;H04N19/85 主分类号 H04N19/70
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