| 摘要 |
<p>A code translation circuit with first shift-register (11, 12 ... 1n) having 4 bits X N stages for storing the operated result BCD data 4 bits by 4 bits from LSD, and second shift register (21, 22 ... 2m) having 4 bits X M stages for storing a BIN data to be translated 4 bits by 4 bits from MSD. A buffer stores the output from the first shift-register (11, 12, ... 1n) and the intermediate result, and output thereof is supplied to and arithmetic/logic circuit (6) through a first selector (3). The output of the second shift-register (21, 22, ... 2m) is selected by a second selector (4) to be supplied to the arithmetic/logic circuit (6). The arithmetic/logic circuit (6) performs X 16 operation for the stored data in the first shift register (11, 12, ... 1n), and adds the result to 4 bits data stored in the shift-register (21, 22 ... 2m) with carry process. The output of the arithmetic/logic circuit (6) is stored in the buffer (5) in the first half of the shift clock (SCK1), and stored in the shift-register (11, 12, ... 1n) in the latter half of the shift clock (SCK1). The shift-register (11, 12, ... 1n) makes a round, while the shift-register 21, 22, ... 2m) is 1 stage shifted. <IMAGE></p> |
