发明名称 |
Instruction dependency chain indentifier |
摘要 |
A method and apparatus for identifying a sequence of instructions that generate data used by an instruction in a programmed flow of instructions includes a bit array of i lines, where i is an integer, each line representing an instruction in an ordered sequence of instructions. A line in the bit array is made up of a string of bits in which a bit position is set corresponding to a preceding instruction that the instruction is dependent upon. Logic coupled to the bit array generates the string of bits for the next instruction by setting bit positions which correspond to directly dependent instructions and additional bit positions corresponding to the predecessor instructions. |
申请公布号 |
US5710902(A) |
申请公布日期 |
1998.01.20 |
申请号 |
US19950524065 |
申请日期 |
1995.09.06 |
申请人 |
INTEL CORPORATION |
发明人 |
SHEAFFER, GAD S.;VALENTINE, ROBERT |
分类号 |
G06F9/38;(IPC1-7):G06F9/38 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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