| 摘要 |
PROBLEM TO BE SOLVED: To enable reduction of electric resistance value of gate wiring while restraining increase of chip size, by connecting the respective word lines to additional wiring patterns from contact holes, on a field shield gate pattern, every one bit. SOLUTION: An oxide film 113 and a polycrystalline silicon layer 112 are patterned in order, and a gate electrode is formed by using the polycrystalline silicon layer 112. An oxide film is deposited on the whole surface, anisotropic etching is performed to the oxide film, and a side wall oxide film 15 is formed on the side surface of the polycrystalline silicon layer 112 as the gate electrode. Then word lines WL1 and WL2 are formed on an element isolation region 127 and a field shield gate pattern 107, respectively. After that, impurities are ion-implanted in the main surface of a silicon semiconductor substrate 101 via an exposed oxide film 110 and diffused, thereby forming a source/drain diffusion layer 116. |
