发明名称 DIGITAL PLL CIRCUIT
摘要 PROBLEM TO BE SOLVED: To use the frequency of an optical integer-multiple compared with the frequency of a reference clock signal by preparing a digital VCO having an addition number variable counter circuit and a circuit which generates a synchronous reproduction clock signal, based on the output pulse signal of the VCO. SOLUTION: A phase comparator 2 outputs a signal, in accordance with the difference between the phase ϕin of an input pulse signal fin and the phase ϕout of a synchronous reproduction clock signal. The signal outputted from the comparator 2 is equal to 1 and 0, when the phase ϕin is larger and smaller than the phase ϕout, respectively. An LPF counter 4 performs the up-counting and down-counting operations, when the output of the compactor 2 is equal to 1 and 0 respectively and then outputs a carrying signal CA and a borrow signal BO when the count value is larger than the 1st set value and smaller than the 2nd set value, respectively. A digital VCO outputs a pulse signal fc±Δf of the frequency, according to the set addition number. Then a 1/N counter 8 outputs a reproduction clock signal, based on the signal fc±Δf.
申请公布号 JPH1013218(A) 申请公布日期 1998.01.16
申请号 JP19960157930 申请日期 1996.06.19
申请人 SONY CORP 发明人 TAKEUCHI ISAO
分类号 H03K23/66;H03L7/06;H03L7/089 主分类号 H03K23/66
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