| 摘要 |
PROBLEM TO BE SOLVED: To provide a complete CMOS type SRAM which is improved in the soft error resistance of a memory cell due to αrays. SOLUTION: A three-dimensional capacity element C1 is formed of the drain area (p type semiconductor layer 18P) of a load MISFET Qp1 , a dielectric film 23, and a plate electrode 24 arranged above a grooveshaped connection hole 19b which electrically connects the gate electrode 17A of a load MISFET QP2 , the gate electrode 6 of a driving MISFET Qd2 , and the drain area (n<+> semiconductor area 8) of a driving MISFET Qd1 . |
