发明名称 |
Synchronized clock using a non-pullable reference oscillator |
摘要 |
Digital signal processing techniques are used to synthesize a range of output frequencies locked to a non-pullable reference oscillator, and the synthesized output frequency is used in a slave low bandwidth phase-locked loop; by increasing digital resolution in a phase accumulation register, any desired resolution of output frequencies can be generated. The range of output frequencies is synthesized in such a way as to generate only high-frequency jitter, which can be easily filtered by follow-on, low-cost, relatively high bandwidth phase-locked loops which are typically needed for frequency multiplication in a given system. The magnitude of residual jitter is easily controlled by proper choice of the non-pullable oscillator reference frequency, the output frequency range to be synthesized and various other digital factors, such as divider ratios. Improved noise performance is achieved while still maintaining a wide pulling range of the composite phase-locked loop.
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申请公布号 |
US5708687(A) |
申请公布日期 |
1998.01.13 |
申请号 |
US19960674422 |
申请日期 |
1996.07.02 |
申请人 |
ALCATEL NETWORK SYSTEMS, INC. |
发明人 |
POWELL, WILLIAM E.;RIEDER, KLAUS-HARTWIG;HOERSCH, GUENTER |
分类号 |
H03L7/099;H03L7/18;H03L7/197;H03L7/23;H04L7/033;(IPC1-7):H03D3/24 |
主分类号 |
H03L7/099 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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