发明名称 |
Process for providing electrostatic discharge protection to an integrated circuit output pad |
摘要 |
An integrated circuit structure with input/output gate voltage regulation and parasitic zener and junction diodes for protection against damage resulting from electrostatic discharge (ESD) events. The circuit includes a first protective FET connected between an input/output pad and a ground potential of the integrated circuit. A diode voltage regulator is also connected between the gate of the first protective FET and a reference potential of the integrated circuit. The first protective FET receives a voltage from its gate-drain overlap capacitance during an ESD event. The diode is operative during an ESD event to provide a sufficient voltage to the first FET gate to permit a desired ESD current flow through the first protective FET. In one embodiment the first FET is an NMOS device and the diode voltage regulator is a series of p-n forward biased diodes.
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申请公布号 |
US5707886(A) |
申请公布日期 |
1998.01.13 |
申请号 |
US19960712896 |
申请日期 |
1996.09.12 |
申请人 |
LSI LOGIC CORPORATION |
发明人 |
CONSIGLIO, ROSARIO;SPARACINO, GINA M. |
分类号 |
H01L27/02;H02H9/04;H03K19/003;(IPC1-7):H01L21/70 |
主分类号 |
H01L27/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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