发明名称 |
Integrated circuitry for checking the utilization rate of redundancy memory elements in a semiconductor memory device |
摘要 |
An apparatus identifies redundancy memory cells that are selected to replace defective memory cells of a memory matrix that communicates with a data bus. A redundancy address register is associated with one of the redundancy memory cells. The redundancy address register stores a default state until it is programmed with an address of one of the defective memory cells. A control circuit generates a test signal during an identification mode. A detect circuit is coupled to the control circuit and to the redundancy address register and generates a default-detect signal in response to the test signal when the redundancy address register contains the default state. A data-bus multiplexer that is coupled to the redundancy-cell selection circuit, the data bus, and the control circuit couples the default detect signal to the data bus in response to the test signal.
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申请公布号 |
US5708601(A) |
申请公布日期 |
1998.01.13 |
申请号 |
US19960602237 |
申请日期 |
1996.02.16 |
申请人 |
SGS-THOMSON MICROELECTRONICS S.R.L. |
发明人 |
MCKENNY, VERNON G.;PASCUCCI, LUIGI;MACCARRONE, MARCO |
分类号 |
G11C29/00;(IPC1-7):G11C7/00 |
主分类号 |
G11C29/00 |
代理机构 |
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主权项 |
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地址 |
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