Steuerschaltung zum Testen eines Abfragepfades

摘要

The control circuit enables not only a flipflop's scan path to be tested, but also the operation of its set and reset terminals. In test mode, the scan path is so configured to form a shift register, in which test data are shifted through the scan path, these shifted data then being used to verify normal operation. During testing, data is fetched using a first clock (CL), when the test enable signal (SMC) is active, and shifted data output using a second clock (CL2). The test control circuit is so configured that neither the set nor reset terminals of the scan path flipflop are active during scan shifting, the test of these being performed by a validation signal (CTL=1) after scan shifting has been completed. In addition, the control circuit generates a signal which inhibits set/reset operations when CL1 and CL2 are active simultaneously.