The present invention provides for a bus bridge circuit (206) having a memory port (4) integrated therewith for upstream memory access independent of the activity on a primary bus (252) connected to the bridge circuit. In a preferred embodiment, the present invention adds a memory port (4) to a PCI bridge circuit (206) usable for upstream data transfers to an attached cache memory subsystem. The memory port (4) of the present invention is preferably 64 bits wide to permit high speed data access to the shared cache memory subsystem. An alternative embodiment of the present invention implements a 128 bit wide data path to an attached high speed cached memory subsystem. The memory port (4) of the present invention utilizes FIFO devices (310) to isolate the memory port transactions from the secondary bus transactions. This FIFO design of the memory port (4) allows bursting of high speed transfers to the shared memory, independent of activity on the primary bus (252), while minimizing the performance impact on a secondary bus (256).
