FET INPUT/OUTPUT PAD LAYOUT

摘要

An object of the present invention is to provide a power FET hard to generate oscillations dependent on the interval between adjacent pads. The present invention has a plurality of pads for first terminals, which are placed in one side on a chip at unequal intervals, and a plurality of pads for second terminals, which are placed in the other side on the chip. Thus, the power FET is hard to generate the oscillations dependent on the interval between the adjacent pads.